whitequark 4b3a068b15 hdl.mem: use 1 as reset value for ReadPort.en. ... This is necessary for consistency, since for transparent read ports, we currently do not support .en at all (it is fixed at 1) due to YosysHQ/yosys#760. Before this commit, changing port transparency would require adding or removing an assignment to .en, which is confusing and error-prone. Also, most read ports are always enabled, so this behavior is also convenient.		2019-09-20 19:51:13 +00:00
..
back	hdl.ast: rename nbits to width.	2019-09-20 15:36:25 +00:00
build	build.plat: bypass tool detection if NMIGEN_*_env is set.	2019-09-12 21:56:48 +00:00
compat	lib.cdc: make domain properties private.	2019-09-12 13:54:48 +00:00
hdl	hdl.mem: use 1 as reset value for ReadPort.en.	2019-09-20 19:51:13 +00:00
lib	lib.fifo: adjust for new CDC primitive conventions.	2019-09-13 12:36:51 +00:00
test	hdl.mem: use 1 as reset value for ReadPort.en.	2019-09-20 19:51:13 +00:00
vendor	vendor.lattice_{ecp5,ice40}: allow clock constraints on arbitrary signals.	2019-09-20 16:26:27 +00:00
__init__.py	Remove nmigen.lib from prelude.	2019-09-06 06:53:06 +00:00
_toolchain.py	_toolchain,build.plat,vendor.*: add required_tools list and checks.	2019-08-31 00:05:47 +00:00
asserts.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: fix typo.	2019-08-19 20:20:18 +00:00