whitequark 015998eba9 hdl.dsl: add clock domain support.		2018-12-16 23:51:24 +00:00
..
__init__.py	compat.fhdl.bitcontainer: import/wrap Migen code.	2018-12-12 15:22:34 +00:00
bitcontainer.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
module.py	hdl.dsl: add clock domain support.	2018-12-16 23:51:24 +00:00
specials.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
structure.py	compat.fhdl.structure: only convert to bool in If/Elif if necessary.	2018-12-16 17:41:42 +00:00