Adam Greig 560bb007cc Give the top level scope a name to fix VCD hierarchy.		2019-01-06 00:10:37 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	Give the top level scope a name to fix VCD hierarchy.	2019-01-06 00:10:37 +00:00
rtlil.py	back.rtlil: translate empty slices correctly.	2019-01-02 18:14:29 +00:00
verilog.py	back.verilog: do not rename internal signals.	2018-12-22 00:53:40 +00:00