whitequark 7c322e562a back.rtlil: extend shorter operand of a binop when matching sign. ... This is necessary because converting a large unsigned value to a signed value of the same width may change its sign. Fixes #271.		2019-11-18 10:39:55 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00
rtlil.py	back.rtlil: extend shorter operand of a binop when matching sign.	2019-11-18 10:39:55 +00:00
verilog.py	back.verilog: remove $verilog_initial_trigger after proc_prune.	2019-10-28 10:11:41 +00:00