whitequark 5702767263 back.rtlil: emit dummy logic to work around Verilog deficiencies.		2018-12-23 10:14:42 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.xfrm: Abstract*Transformer→*Visitor	2018-12-22 06:03:39 +00:00
rtlil.py	back.rtlil: emit dummy logic to work around Verilog deficiencies.	2018-12-23 10:14:42 +00:00
verilog.py	back.verilog: do not rename internal signals.	2018-12-22 00:53:40 +00:00