whitequark 99b778158d compat: use nicer names for next_value/next_value_ce signals.		2018-12-22 02:05:49 +00:00
..
fhdl	compat: fix confusing naming for memory port address signal.	2018-12-22 00:53:05 +00:00
genlib	compat: use nicer names for next_value/next_value_ce signals.	2018-12-22 02:05:49 +00:00
sim	back.pysim: make initial phase configurable.	2018-12-14 16:46:16 +00:00
__init__.py	compat: import genlib.record from Migen.	2018-12-18 20:04:22 +00:00