whitequark 59c7540aeb back.rtlil: split processes as finely as possible. ... This makes simulation work correctly (by introducing delta cycles, and therefore, making the overall Verilog simulation deterministic) at the price of pessimizing mux trees generated by Yosys and Synplify frontends, sometimes severely.		2018-12-22 10:03:16 +00:00
..
back	back.rtlil: split processes as finely as possible.	2018-12-22 10:03:16 +00:00
compat	compat: use nicer names for next_value/next_value_ce signals.	2018-12-22 02:05:49 +00:00
hdl	hdl.xfrm: implement LHSGroupAnalyzer.	2018-12-22 06:58:24 +00:00
lib	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
test	hdl.xfrm: implement LHSGroupAnalyzer.	2018-12-22 06:58:24 +00:00
__init__.py	hdl.mem: implement memories.	2018-12-21 01:53:32 +00:00
tools.py	compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.	2018-12-18 20:03:32 +00:00
tracer.py	compat: import genlib.record from Migen.	2018-12-18 20:04:22 +00:00