whitequark 5c626e33bf compat.fhdl.module: fix finalization of transformed compat submodules. ... Before this commit, the TransformedElaboratable of a CompatModule would be ignored, and .get_fragment() would be used to retrieve the CompatModule within. After this commit, the finalization process is reworked to match oMigen's finalization closely, and all submodules, native and compat, are added in the same way that preserves applied transforms.		2019-08-08 07:45:34 +00:00
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back	back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS.	2019-08-04 00:12:08 +00:00
build	vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic.	2019-08-04 23:28:09 +00:00
compat	compat.fhdl.module: fix finalization of transformed compat submodules.	2019-08-08 07:45:34 +00:00
hdl	hdl.dsl: reword m.If(~True) warning to be more clear.	2019-08-03 18:52:24 +00:00
lib	lib.fifo: fix typo.	2019-07-15 14:12:33 +00:00
test	hdl.dsl: reword m.If(~True) warning to be more clear.	2019-08-03 18:52:24 +00:00
vendor	vendor.lattice_ice40: add iCE5LP2K support.	2019-08-07 09:25:20 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: add PyPy support to get_var_name().	2019-07-09 07:29:01 +00:00