amaranth/nmigen/hdl
whitequark 649444449d hdl.ast: make Signal(name=) a keyword-only argument.
Almost no code would specify Signal(_, name) as a positional argument
on purpose, but forgetting parens and accidentally placing signedness
into the name position is so common that we had a test for it.
2019-09-23 11:08:43 +00:00
..
__init__.py hdl.xfrm: CEInserter→EnableInserter. 2019-08-12 13:39:26 +00:00
ast.py hdl.ast: make Signal(name=) a keyword-only argument. 2019-09-23 11:08:43 +00:00
cd.py hdl.cd: add negedge clock domains. 2019-08-31 22:05:48 +00:00
dsl.py hdl.ast: rename nbits to width. 2019-09-20 15:36:25 +00:00
ir.py build.plat, hdl.ir: coordinate missing domain creation. 2019-08-19 22:52:01 +00:00
mem.py hdl.mem: use 1 as reset value for ReadPort.en. 2019-09-20 19:51:13 +00:00
rec.py hdl.rec: fix using Enum subclass as shape if direction is specified. 2019-09-22 17:23:32 +00:00
xfrm.py hdl.ast: rename nbits to width. 2019-09-20 15:36:25 +00:00