whitequark d964ba9cc4 build,vendor: never carry around parts of differential signals. ... When a port component is skipped, it should appear neither in the RTL nor in the constraint file. However, passing around components of differential ports explicitly makes that harder. Fixes #456. Supersedes #457. Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>		2020-07-31 18:41:59 +00:00
..
__init__.py	build.{dsl,res,plat}: apply clock constraints to signals, not resources.	2019-06-05 08:52:30 +00:00
dsl.py	build.dsl: allow strings to be used as connector numbers.	2020-01-31 03:11:34 +00:00
plat.py	build,vendor: never carry around parts of differential signals.	2020-07-31 18:41:59 +00:00
res.py	build,vendor: never carry around parts of differential signals.	2020-07-31 18:41:59 +00:00
run.py	Clarify a few comments. NFC.	2020-04-13 13:55:23 +00:00