whitequark 6672ab2e3f back.rtlil: explicitly pad constants with zeroes. ... I'm not sure what exactly RTLIL does when a constant isn't as long as its bit width, and there's no reason to keep the ambiguity.		2018-12-21 01:51:18 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.ast: Cat.{operands→parts}	2018-12-18 19:15:50 +00:00
rtlil.py	back.rtlil: explicitly pad constants with zeroes.	2018-12-21 01:51:18 +00:00
verilog.py	back.verilog: remove debug code.	2018-12-13 13:42:54 +00:00