whitequark 70f3563b5f back.rtlil: attach source locations to switches, not processes. ... This effectively reverts and reimplements half of commit 82903e49. I was confused and did not realize that RTLIL does, in fact, have attributes on switches. After this commit, processes no longer have any source locations. This is semantically fine, as the processes we emit are purely artificial (because of LHS grouping), but I have not checked how downstream tooling handles this.		2019-07-08 09:10:09 +00:00
..
back	back.rtlil: attach source locations to switches, not processes.	2019-07-08 09:10:09 +00:00
build	build.plat: source a script with toolchain environment.	2019-07-07 00:44:28 +00:00
compat	compat.fhdl.specials: mark CompatMemory as Elaboratable.	2019-07-03 13:28:57 +00:00
hdl	hdl.dsl: further clarify error message for incorrect nesting.	2019-07-07 01:03:59 +00:00
lib	hdl.mem: use read_port(domain="comb") for asynchronous read ports.	2019-07-01 19:56:49 +00:00
test	hdl.dsl: further clarify error message for incorrect nesting.	2019-07-07 01:03:59 +00:00
vendor	vendor.xilinx_7series: generate also binary bitfile.	2019-07-07 21:36:32 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00