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amaranth/nmigen/back
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whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
2019-06-28 04:37:08 +00:00
..
__init__.py Initial commit. 2018-12-12 03:18:44 +00:00
pysim.py hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 2019-06-28 04:37:08 +00:00
rtlil.py hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 2019-06-28 04:37:08 +00:00
verilog.py back.verilog: allow stripping the src attribute, for cleaner output. 2019-04-22 14:59:53 +00:00