whitequark 779f3ee906 lib.cdc: avoid interior clock domains in ResetSynchronizer. ... Such clock domains will "leak" into the enclosing scope, which is generally undesirable. Also, this is instructive for a platform overriding the behavior, since it provides guidance on how to correctly instantiate platform-specific flops. I've considered also doing this for MultiReg(), but it is very challenging in presence of non-reset-less CDC FFs, since Yosys' $dffsr primitive has separate set and clear inputs, and reshuffling the reset value for those results in quite a bit of additional logic. (That said, it might have to be done anyway, precisely because letting Yosys generate this additional logic might prove too much for the toolchain to cope with, and again, platform-independent code should provide guidance to platform-specific code.)		2019-06-28 07:34:10 +00:00
..
back	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
build	build.plat: fix dedent overrides.	2019-06-28 06:52:52 +00:00
compat	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
hdl	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
lib	lib.cdc: avoid interior clock domains in ResetSynchronizer.	2019-06-28 07:34:10 +00:00
test	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
vendor	vendor.lattice_ice40: fix instance of negedge FF due to a typo.	2019-06-28 07:05:20 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00