whitequark 792f35ac8f back.rtlil: refuse to create extremely large wires. ... Such wires are likely to trigger pathological behavior in Yosys and, if applicable, other toolchains that consume Verilog converted from RTLIL. Fixes #341.		2020-04-13 16:38:36 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: Clear pending updates after they are effected	2020-04-08 14:08:35 +00:00
rtlil.py	back.rtlil: refuse to create extremely large wires.	2020-04-13 16:38:36 +00:00
verilog.py	back.verilog: remove $verilog_initial_trigger after proc_prune.	2019-10-28 10:11:41 +00:00