whitequark 792f35ac8f back.rtlil: refuse to create extremely large wires. ... Such wires are likely to trigger pathological behavior in Yosys and, if applicable, other toolchains that consume Verilog converted from RTLIL. Fixes #341.		2020-04-13 16:38:36 +00:00
..
back	back.rtlil: refuse to create extremely large wires.	2020-04-13 16:38:36 +00:00
build	Clarify a few comments. NFC.	2020-04-13 13:55:23 +00:00
compat	Add support for using non-compat Elaboratable instances with compat.fhdl.verilog.convert and compat.run_simulation	2020-04-02 02:46:44 +00:00
hdl	hdl.ast: add Value.{rotate_left,rotate_right}.	2020-04-13 13:40:39 +00:00
lib	Correctly handle resets in AsyncFIFO.	2020-03-14 23:26:07 +00:00
test	hdl.ast: add Value.{rotate_left,rotate_right}.	2020-04-13 13:40:39 +00:00
vendor	vendor.lattice_ice40: add support for SB_[LH]FOSC as default_clk.	2020-03-20 08:10:48 +00:00
__init__.py	Remove everything deprecated in nmigen 0.1.	2020-01-12 13:59:26 +00:00
_toolchain.py	Refactor build script toolchain lookups.	2019-10-13 13:53:24 +00:00
_unused.py	_unused: extract must-use logic from hdl.ir.	2020-02-01 01:35:05 +00:00
_utils.py	hdl.ir: allow disabling UnusedElaboratable warning in file scope.	2019-10-26 06:17:14 +00:00
asserts.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00
cli.py	cli: update use of deprecated code.	2020-02-12 14:42:24 +00:00
rpc.py	rpc: add public Records as module ports.	2019-09-30 18:28:21 +00:00
tracer.py	tracer: fix typo.	2019-08-19 20:20:18 +00:00
utils.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00