amaranth/nmigen
whitequark 8050cfaa98 build.res: simplify clock constraints.
Before this commit, it was possible to set and get clock constraints
placed on Pin objects. This was not a very good implementation, since
it relied on matching the identity of the provided Pin object to
a previously requested one. The only reason it worked like that is
deficiencies in nextpnr.

Since then, nextpnr has been fixed to allow setting constraints on
arbitrary nets. Correspondingly, backends that are using Synplify
were changed to use [get_nets] instead of [get_ports] in SDC files.
However, in some situations, Synplify does not allow specifying
ports in [get_nets]. (In fact, nextpnr had a similar problem, but
it has also been fixed.)

The simplest way to address this is to refer to the interior net
(after the input buffer), which always works. The only downside
of this is that requesting a clock as a raw pin using
    platform.request("clk", dir="-")
and directly applying a constraint to it could fail in some cases.
This is not a significant issue.
2019-09-21 14:12:29 +00:00
..
back hdl.ast: rename nbits to width. 2019-09-20 15:36:25 +00:00
build build.res: simplify clock constraints. 2019-09-21 14:12:29 +00:00
compat lib.cdc: make domain properties private. 2019-09-12 13:54:48 +00:00
hdl hdl.ast: update docs. NFC. 2019-09-21 06:53:13 +00:00
lib lib.fifo: update docs. NFC. 2019-09-21 06:53:57 +00:00
test build.res: simplify clock constraints. 2019-09-21 14:12:29 +00:00
vendor build.plat: NMIGEN_<toolchain>_env→NMIGEN_ENV_<toolchain> 2019-09-21 12:23:53 +00:00
__init__.py Remove nmigen.lib from prelude. 2019-09-06 06:53:06 +00:00
_toolchain.py _toolchain,build.plat,vendor.*: add required_tools list and checks. 2019-08-31 00:05:47 +00:00
asserts.py hdl.ast,back.rtlil: implement Cover. 2019-09-03 01:32:24 +00:00
cli.py hdl.ir: rename .get_fragment() to .elaborate(). 2019-01-26 02:31:12 +00:00
tools.py hdl: make all public Value classes other than Record final. 2019-05-12 05:40:17 +00:00
tracer.py tracer: fix typo. 2019-08-19 20:20:18 +00:00