whitequark 82903e493a back.rtlil: emit \src attributes for processes via Switch and Assign. ... The locations are unfortunately not very precise, but they provide some improvement over status quo.		2019-07-03 16:27:54 +00:00
..
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
ast.py	back.rtlil: emit \src attributes for processes via Switch and Assign.	2019-07-03 16:27:54 +00:00
cd.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
dsl.py	back.rtlil: emit \src attributes for processes via Switch and Assign.	2019-07-03 16:27:54 +00:00
ir.py	hdl.ir, back.rtlil: allow specifying attributes on instances.	2019-06-28 04:14:38 +00:00
mem.py	hdl.mem: fix naming of registers inside unnamed memories.	2019-07-02 18:45:35 +00:00
rec.py	hdl.rec: thread src_loc_at to all inner Signals and Records.	2019-07-03 14:49:20 +00:00
xfrm.py	back.rtlil: emit \src attributes for processes via Switch and Assign.	2019-07-03 16:27:54 +00:00