amaranth/nmigen/test
whitequark ed7e07c6c1 hdl.ast: implement Initial.
This is the last remaining part for first-class formal support.
2019-08-15 02:53:07 +00:00
..
compat compat: suppress deprecation warnings that are internal or during test. 2019-01-26 15:43:00 +00:00
__init__.py hdl.ir: detect elaboratables that are created but not used. 2019-04-21 08:52:57 +00:00
test_build_dsl.py build.dsl: Add optional name_suffix to Resource.family. 2019-07-10 15:41:23 +00:00
test_build_res.py build.res: detect physical conflicts earlier. 2019-07-03 15:07:44 +00:00
test_compat.py compat.fhdl.module: CompatModule should be elaboratable. 2019-06-04 11:11:31 +00:00
test_examples.py hdl.xfrm: CEInserter→EnableInserter. 2019-08-12 13:39:26 +00:00
test_hdl_ast.py hdl.ast: implement Initial. 2019-08-15 02:53:07 +00:00
test_hdl_cd.py hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain. 2019-07-08 10:26:49 +00:00
test_hdl_dsl.py hdl.dsl: reword m.If(~True) warning to be more clear. 2019-08-03 18:52:24 +00:00
test_hdl_ir.py hdl.ir: allow adding more than one domain in missing domain callback. 2019-08-03 18:19:40 +00:00
test_hdl_mem.py hdl.mem: use read_port(domain="comb") for asynchronous read ports. 2019-07-01 19:56:49 +00:00
test_hdl_rec.py hdl.rec: respect modifications to signals in Record.like(). 2019-07-08 10:59:15 +00:00
test_hdl_xfrm.py hdl.xfrm: CEInserter→EnableInserter. 2019-08-12 13:39:26 +00:00
test_lib_cdc.py Clean up imports. 2019-06-04 08:18:50 +00:00
test_lib_coding.py Clean up imports. 2019-06-04 08:18:50 +00:00
test_lib_fifo.py hdl.ast: implement Initial. 2019-08-15 02:53:07 +00:00
test_lib_io.py Clean up imports. 2019-06-04 08:18:50 +00:00
test_sim.py hdl.ir: call back from Fragment.prepare if a clock domain is missing. 2019-08-03 14:54:20 +00:00
tools.py hdl.xfrm: handle mem.{Read,Write}Port in CEInserter. 2019-07-31 05:20:05 +00:00