whitequark 6ee80408bb back.verilog: do not rename internal signals. ... _0_ is not really any better than \$13, and the latter at least has continuity between nMigen, RTLIL and Verilog.		2018-12-22 00:53:40 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: handle out of bounds ArrayProxy indexes.	2018-12-21 12:32:08 +00:00
rtlil.py	back.rtlil: more consistent prefixing for subfragment port wires.	2018-12-21 04:21:11 +00:00
verilog.py	back.verilog: do not rename internal signals.	2018-12-22 00:53:40 +00:00