whitequark 8854ca03ae build.plat,vendor: automatically create sync domain from default_clk. ... But only if it is not defined by the programmer. Closes #57.		2019-08-03 18:36:58 +00:00
..
back	back.rtlil: fix sim-synth mismatch with assigns following switches.	2019-08-03 13:27:47 +00:00
build	build.plat,vendor: automatically create sync domain from default_clk.	2019-08-03 18:36:58 +00:00
compat	hdl.ir: call back from Fragment.prepare if a clock domain is missing.	2019-08-03 14:54:20 +00:00
hdl	hdl.ir: allow adding more than one domain in missing domain callback.	2019-08-03 18:19:40 +00:00
lib	lib.fifo: fix typo.	2019-07-15 14:12:33 +00:00
test	hdl.ir: allow adding more than one domain in missing domain callback.	2019-08-03 18:19:40 +00:00
vendor	build.plat,vendor: automatically create sync domain from default_clk.	2019-08-03 18:36:58 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: add PyPy support to get_var_name().	2019-07-09 07:29:01 +00:00