whitequark 066dd799e8 back.pysim: check for a clock being added twice. ... This commit adds a best-effort error for a common mistake of adding a clock driving the same domain twice, such as a result of a copy-paste error. Fixes #27.		2019-06-11 03:54:22 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: check for a clock being added twice.	2019-06-11 03:54:22 +00:00
rtlil.py	back.rtlil: mask memory init values.	2019-06-11 03:43:09 +00:00
verilog.py	back.verilog: allow stripping the src attribute, for cleaner output.	2019-04-22 14:59:53 +00:00