amaranth/nmigen
whitequark 8c6c3643cd sim._pyrtl: optimize uses of reflexive operators.
When a literal is used on the left-hand side of a numeric operator,
Python is able to constant-fold some expressions:

    >>> dis.dis(lambda x: 0 + 0 + x)
      1           0 LOAD_CONST               1 (0)
                  2 LOAD_FAST                0 (x)
                  4 BINARY_ADD
                  6 RETURN_VALUE

If a literal is used on the right-hand side such that the left-hand
side is variable, this doesn't happen:

    >>> dis.dis(lambda x: x + 0 + 0)
      1           0 LOAD_FAST                0 (x)
                  2 LOAD_CONST               1 (0)
                  4 BINARY_ADD
                  6 LOAD_CONST               1 (0)
                  8 BINARY_ADD
                 10 RETURN_VALUE

PyRTL generates fairly redundant code due to the pervasive masking,
and because of that, transforming expressions into the former form,
where possible, improves runtime by about 10% on Minerva SRAM SoC.
2020-08-26 13:26:58 +00:00
..
_toolchain _yosys→_toolchain.yosys 2020-07-02 18:26:08 +00:00
back back.cxxrtl: actualize Yosys version requirement. 2020-08-26 09:16:46 +00:00
build build,vendor: never carry around parts of differential signals. 2020-07-31 18:41:59 +00:00
compat nmigen.lib.scheduler: add RoundRobin. 2020-07-28 21:02:01 +00:00
hdl hdl.ast: avoid unnecessary sign padding in ArrayProxy. 2020-08-26 07:07:48 +00:00
lib lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=. 2020-08-26 03:19:13 +00:00
sim sim._pyrtl: optimize uses of reflexive operators. 2020-08-26 13:26:58 +00:00
test hdl.ast: avoid unnecessary sign padding in ArrayProxy. 2020-08-26 07:07:48 +00:00
vendor lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=. 2020-08-26 03:19:13 +00:00
__init__.py Gracefully handle missing dependencies. 2020-07-01 07:00:02 +00:00
_unused.py _unused: extract must-use logic from hdl.ir. 2020-02-01 01:35:05 +00:00
_utils.py hdl.ir: allow disabling UnusedElaboratable warning in file scope. 2019-10-26 06:17:14 +00:00
asserts.py hdl.ast,back.rtlil: implement Cover. 2019-09-03 01:32:24 +00:00
cli.py cli: Improve help texts 2020-08-22 14:41:37 +00:00
rpc.py rpc: add public Records as module ports. 2019-09-30 18:28:21 +00:00
tracer.py tracer: fix get_var_name() to work on toplevel attributes. 2020-05-17 19:51:58 +00:00
utils.py {,_}tools→{,_}utils 2019-10-13 18:53:38 +00:00