whitequark 00ef7a78d3 compat: provide verilog.convert shim.		2018-12-21 13:53:06 +00:00
..
__init__.py	compat.fhdl.bitcontainer: import/wrap Migen code.	2018-12-12 15:22:34 +00:00
bitcontainer.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
conv_output.py	compat: provide verilog.convert shim.	2018-12-21 13:53:06 +00:00
module.py	hdl.dsl: add clock domain support.	2018-12-16 23:51:24 +00:00
specials.py	compat: provide Memory shim.	2018-12-21 13:15:52 +00:00
structure.py	compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.	2018-12-18 20:03:32 +00:00
verilog.py	compat: provide verilog.convert shim.	2018-12-21 13:53:06 +00:00