whitequark 913339c04a hdl.ir: fix port propagation between siblings.		2018-12-21 23:53:18 +00:00
..
__init__.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
ast.py	hdl.mem: implement memories.	2018-12-21 01:53:32 +00:00
cd.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
dsl.py	hdl, back: add and use SignalSet/SignalDict.	2018-12-17 17:21:29 +00:00
ir.py	hdl.ir: fix port propagation between siblings.	2018-12-21 23:53:18 +00:00
mem.py	hdl.mem: ensure transparent read port model has correct latency.	2018-12-21 13:01:08 +00:00
xfrm.py	ir: allow non-Signals in Instance ports.	2018-12-20 23:40:40 +00:00