| .. |
|
compat
|
lib.fifo: adjust properties to have consistent naming.
|
2019-09-13 12:33:41 +00:00 |
|
__init__.py
|
hdl.ir: detect elaboratables that are created but not used.
|
2019-04-21 08:52:57 +00:00 |
|
test_build_dsl.py
|
build.dsl: allow both str and int resource attributes.
|
2019-08-30 08:35:52 +00:00 |
|
test_build_res.py
|
build.res: simplify clock constraints.
|
2019-09-21 14:12:29 +00:00 |
|
test_compat.py
|
compat.fhdl.module: CompatModule should be elaboratable.
|
2019-06-04 11:11:31 +00:00 |
|
test_examples.py
|
test.test_examples: Convert pathlib-specific class to string.
|
2019-08-20 00:54:10 +00:00 |
|
test_hdl_ast.py
|
hdl.ast: don't crash on Mux(<bool>, ...).
|
2019-10-02 08:30:15 +00:00 |
|
test_hdl_cd.py
|
hdl.cd: add negedge clock domains.
|
2019-08-31 22:05:48 +00:00 |
|
test_hdl_dsl.py
|
hdl.dsl: add a diagnostic for m.d.submodules += ....
|
2019-09-28 17:50:24 +00:00 |
|
test_hdl_ir.py
|
build.plat, hdl.ir: coordinate missing domain creation.
|
2019-08-19 22:52:01 +00:00 |
|
test_hdl_mem.py
|
hdl.mem: remove WritePort(priority=) argument.
|
2019-09-28 01:29:56 +00:00 |
|
test_hdl_rec.py
|
hdl.rec: fix using Enum subclass as shape if direction is specified.
|
2019-09-22 17:23:32 +00:00 |
|
test_hdl_xfrm.py
|
hdl.xfrm: lower resets in DomainLowerer as well.
|
2019-08-19 21:44:30 +00:00 |
|
test_lib_cdc.py
|
lib.cdc: add diagnostic checks for synchronization stage count.
|
2019-09-23 19:38:21 +00:00 |
|
test_lib_coding.py
|
formal→asserts
|
2019-08-19 20:23:24 +00:00 |
|
test_lib_fifo.py
|
lib.fifo: handle depth=0, elaborating to a dummy FIFO with no logic.
|
2019-09-23 12:27:59 +00:00 |
|
test_lib_io.py
|
Clean up imports.
|
2019-06-04 08:18:50 +00:00 |
|
test_sim.py
|
hdl.ast: actually implement the // operator.
|
2019-09-28 19:33:24 +00:00 |
|
tools.py
|
_toolchain,build.plat,vendor.*: add required_tools list and checks.
|
2019-08-31 00:05:47 +00:00 |
