amaranth/nmigen/hdl
whitequark 585514e6ed hdl.ir: rework named port handling for Instances.
The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.

While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
2019-04-22 07:46:47 +00:00
..
__init__.py Rename fhdl→hdl, genlib→lib. 2018-12-15 14:25:31 +00:00
ast.py hdl.ast: accept Signals with identical min/max bounds. 2019-04-21 07:16:59 +00:00
cd.py Rename fhdl→hdl, genlib→lib. 2018-12-15 14:25:31 +00:00
dsl.py hdl.ir: detect elaboratables that are created but not used. 2019-04-21 08:52:57 +00:00
ir.py hdl.ir: rework named port handling for Instances. 2019-04-22 07:46:47 +00:00
mem.py hdl.ir: detect elaboratables that are created but not used. 2019-04-21 08:52:57 +00:00
rec.py hdl.rec: implement Record.connect. 2019-04-21 06:37:08 +00:00
xfrm.py hdl.ir: rework named port handling for Instances. 2019-04-22 07:46:47 +00:00