whitequark fdb0c5a6bc hdl.ir: call back from Fragment.prepare if a clock domain is missing. ... See #57.		2019-08-03 14:54:20 +00:00
..
__init__.py	compat.fhdl.bitcontainer: import/wrap Migen code.	2018-12-12 15:22:34 +00:00
bitcontainer.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
conv_output.py	compat: provide verilog.convert shim.	2018-12-21 13:53:06 +00:00
module.py	compat.fhdl.module: silence "unused elaboratable" warnings.	2019-06-04 13:09:36 +00:00
specials.py	compat.fhdl.specials: mark CompatMemory as Elaboratable.	2019-07-03 13:28:57 +00:00
structure.py	compat.fhdl.structure: fix If/Elif/Else after 32446831.	2019-07-03 13:19:15 +00:00
verilog.py	hdl.ir: call back from Fragment.prepare if a clock domain is missing.	2019-08-03 14:54:20 +00:00