amaranth/nmigen
whitequark 9bc42cb8c5 sim._pyclock: new type of process.
The overhead of coroutine processes is fairly high. A clock driver
implemented through a coroutine process is mostly overhead. This was
partially addressed in commit 2398b792 by microoptimizing yielding.

This commit eliminates the coroutine process overhead completely by
introducing dedicated clock processes. It also simplifies the logic
to a simple toggle.

This change improves runtime by about 12% on Minerva SRAM SoC.
2020-08-27 07:56:47 +00:00
..
_toolchain _toolchain.cxx: work around PyPy missing LDCXXSHARED sysconfig variable. 2020-08-27 06:53:14 +00:00
back back.rtlil: do not squash empty modules. 2020-08-26 22:45:19 +00:00
build build.run: implement SSH remote builds using Paramiko. 2020-08-26 22:49:49 +00:00
compat nmigen.lib.scheduler: add RoundRobin. 2020-07-28 21:02:01 +00:00
hdl hdl.ast: clarify exception message for out of bounds indexing. 2020-08-27 01:14:05 +00:00
lib lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=. 2020-08-26 03:19:13 +00:00
sim sim._pyclock: new type of process. 2020-08-27 07:56:47 +00:00
test nmigen.test.utils: restore FHDLTestCase to gracefully deprecate it. 2020-08-27 00:46:50 +00:00
vendor vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVICE as appropriate. 2020-08-26 15:45:58 +00:00
__init__.py Gracefully handle missing dependencies. 2020-07-01 07:00:02 +00:00
_unused.py _unused: extract must-use logic from hdl.ir. 2020-02-01 01:35:05 +00:00
_utils.py hdl.ir: allow disabling UnusedElaboratable warning in file scope. 2019-10-26 06:17:14 +00:00
asserts.py hdl.ast,back.rtlil: implement Cover. 2019-09-03 01:32:24 +00:00
cli.py cli: Improve help texts 2020-08-22 14:41:37 +00:00
rpc.py rpc: add public Records as module ports. 2019-09-30 18:28:21 +00:00
tracer.py tracer: fix get_var_name() to work on toplevel attributes. 2020-05-17 19:51:58 +00:00
utils.py {,_}tools→{,_}utils 2019-10-13 18:53:38 +00:00