amaranth/nmigen/back
whitequark 9bce35098f back.rtlil: avoid illegal slices.
Not sure what to do with {} [] on LHS yet--fix Yosys?
2018-12-16 17:41:11 +00:00
..
__init__.py Initial commit. 2018-12-12 03:18:44 +00:00
pysim.py hdl.xfrm: separate AST traversal from AST identity mapping. 2018-12-16 11:25:52 +00:00
rtlil.py back.rtlil: avoid illegal slices. 2018-12-16 17:41:11 +00:00
verilog.py back.verilog: remove debug code. 2018-12-13 13:42:54 +00:00