whitequark 9c28b61d9f hdl.ir: don't expose as ports missing domains added via elaboratables. ... The elaboratable is already likely driving the clk/rst signals in some way appropriate for the platform; if we expose them as ports nevertheless it will cause problems downstream.		2019-08-03 16:39:21 +00:00
..
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
ast.py	hdl.ast: fix typo.	2019-08-03 13:21:09 +00:00
cd.py	hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.	2019-07-08 10:26:49 +00:00
dsl.py	hdl.dsl: warn on suspicious statements like m.If(~True):.	2019-08-03 14:00:29 +00:00
ir.py	hdl.ir: don't expose as ports missing domains added via elaboratables.	2019-08-03 16:39:21 +00:00
mem.py	hdl.{dsl,mem,xfrm}: inject appropriate source locations.	2019-07-08 09:58:12 +00:00
rec.py	hdl.rec: respect modifications to signals in Record.like().	2019-07-08 10:59:15 +00:00
xfrm.py	hdl.ir: call back from Fragment.prepare if a clock domain is missing.	2019-08-03 14:54:20 +00:00