whitequark 9c54d0c061 back.pysim: create unique ResetSynchronizer internal domains. ... Commit 300d47ca introduced the same bug commit 779f3ee9 was trying to avoid, but now only in the simulator. Since the names in simulator don't have to make any sense, just use DUID to generate them.		2019-06-28 08:34:43 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: create unique ResetSynchronizer internal domains.	2019-06-28 08:34:43 +00:00
rtlil.py	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
verilog.py	back.verilog: allow stripping the src attribute, for cleaner output.	2019-04-22 14:59:53 +00:00