whitequark 9c54d0c061 back.pysim: create unique ResetSynchronizer internal domains. ... Commit 300d47ca introduced the same bug commit 779f3ee9 was trying to avoid, but now only in the simulator. Since the names in simulator don't have to make any sense, just use DUID to generate them.		2019-06-28 08:34:43 +00:00
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back	back.pysim: create unique ResetSynchronizer internal domains.	2019-06-28 08:34:43 +00:00
build	build.plat: fix dedent overrides.	2019-06-28 06:52:52 +00:00
compat	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
hdl	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
lib	lib.cdc: avoid interior clock domains in ResetSynchronizer.	2019-06-28 07:34:10 +00:00
test	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
vendor	vendor.lattice_ice40: fix instance of negedge FF due to a typo.	2019-06-28 07:05:20 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00