whitequark a2241fcfdb back.{rtlil,verilog}: split convert_fragment() off convert(). ... Because Fragment.prepare is not (currently) idempotent, it is useful to be able to avoid calling it when converting. Even if it is made idempotent, it can be slow on large designs, so it is advantageous regardless of that.		2019-08-19 19:49:51 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.ast: implement Initial.	2019-08-15 02:53:07 +00:00
rtlil.py	back.{rtlil,verilog}: split convert_fragment() off convert().	2019-08-19 19:49:51 +00:00
verilog.py	back.{rtlil,verilog}: split convert_fragment() off convert().	2019-08-19 19:49:51 +00:00