whitequark a2241fcfdb back.{rtlil,verilog}: split convert_fragment() off convert(). ... Because Fragment.prepare is not (currently) idempotent, it is useful to be able to avoid calling it when converting. Even if it is made idempotent, it can be slow on large designs, so it is advantageous regardless of that.		2019-08-19 19:49:51 +00:00
..
back	back.{rtlil,verilog}: split convert_fragment() off convert().	2019-08-19 19:49:51 +00:00
build	build.dsl: add conn argument to Connector.	2019-08-18 19:56:25 +00:00
compat	back.{rtlil,verilog}: split convert_fragment() off convert().	2019-08-19 19:49:51 +00:00
hdl	hdl.xfrm: make deprecated CEInserter more well-behaved.	2019-08-18 16:26:45 +00:00
lib	hdl.ast: implement Initial.	2019-08-15 02:53:07 +00:00
test	build.dsl: add conn argument to Connector.	2019-08-18 19:56:25 +00:00
vendor	vendor.lattice_ice40: add iCE5LP2K support.	2019-08-07 09:25:20 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	hdl.ast: implement Initial.	2019-08-15 02:53:07 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: use sys._getframe directly.	2019-08-08 10:23:35 +00:00