whitequark a4183eba69 hdl.mem: use more informative signal naming for ports.		2018-12-21 23:55:02 +00:00
..
back	back.pysim: handle out of bounds ArrayProxy indexes.	2018-12-21 12:32:08 +00:00
compat	compat: provide verilog.convert shim.	2018-12-21 13:53:06 +00:00
hdl	hdl.mem: use more informative signal naming for ports.	2018-12-21 23:55:02 +00:00
lib	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
test	hdl.ir: fix port propagation between siblings.	2018-12-21 23:53:18 +00:00
__init__.py	hdl.mem: implement memories.	2018-12-21 01:53:32 +00:00
tools.py	compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.	2018-12-18 20:03:32 +00:00
tracer.py	compat: import genlib.record from Migen.	2018-12-18 20:04:22 +00:00