whitequark af7db882c0 hdl.mem: use different naming for array signals. ... It looks like [] is confusing gtkwave somehow.		2018-12-21 12:26:49 +00:00
..
back	back.pysim: fix an issue with too few funclet slots.	2018-12-21 10:25:28 +00:00
compat	compat: import genlib.record from Migen.	2018-12-18 20:04:22 +00:00
hdl	hdl.mem: use different naming for array signals.	2018-12-21 12:26:49 +00:00
lib	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
test	hdl.mem: add simulation model for memory.	2018-12-21 11:54:32 +00:00
__init__.py	hdl.mem: implement memories.	2018-12-21 01:53:32 +00:00
tools.py	compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.	2018-12-18 20:03:32 +00:00
tracer.py	compat: import genlib.record from Migen.	2018-12-18 20:04:22 +00:00