whitequark b0bd7bfaca hdl.ir: correctly handle named output and inout ports.		2018-12-21 04:03:03 +00:00
..
back	back.rtlil: implement memories.	2018-12-21 01:55:59 +00:00
compat	compat: import genlib.record from Migen.	2018-12-18 20:04:22 +00:00
hdl	hdl.ir: correctly handle named output and inout ports.	2018-12-21 04:03:03 +00:00
lib	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
test	hdl.ir: correctly handle named output and inout ports.	2018-12-21 04:03:03 +00:00
__init__.py	hdl.mem: implement memories.	2018-12-21 01:53:32 +00:00
tools.py	compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.	2018-12-18 20:03:32 +00:00
tracer.py	compat: import genlib.record from Migen.	2018-12-18 20:04:22 +00:00