| .. |
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compat
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lib.fifo: adjust properties to have consistent naming.
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2019-09-13 12:33:41 +00:00 |
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__init__.py
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hdl.ir: detect elaboratables that are created but not used.
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2019-04-21 08:52:57 +00:00 |
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test_build_dsl.py
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build.dsl: allow both str and int resource attributes.
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2019-08-30 08:35:52 +00:00 |
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test_build_res.py
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build.res: simplify clock constraints.
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2019-09-21 14:12:29 +00:00 |
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test_compat.py
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compat.fhdl.module: CompatModule should be elaboratable.
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2019-06-04 11:11:31 +00:00 |
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test_examples.py
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test.test_examples: Convert pathlib-specific class to string.
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2019-08-20 00:54:10 +00:00 |
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test_hdl_ast.py
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hdl.ast: cast Mux() selector to bool if it is not a 1-bit value.
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2019-09-23 13:39:31 +00:00 |
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test_hdl_cd.py
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hdl.cd: add negedge clock domains.
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2019-08-31 22:05:48 +00:00 |
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test_hdl_dsl.py
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hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns.
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2019-09-16 19:22:12 +00:00 |
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test_hdl_ir.py
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build.plat, hdl.ir: coordinate missing domain creation.
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2019-08-19 22:52:01 +00:00 |
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test_hdl_mem.py
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hdl.mem: simplify. NFC.
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2019-09-23 11:16:29 +00:00 |
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test_hdl_rec.py
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hdl.rec: fix using Enum subclass as shape if direction is specified.
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2019-09-22 17:23:32 +00:00 |
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test_hdl_xfrm.py
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hdl.xfrm: lower resets in DomainLowerer as well.
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2019-08-19 21:44:30 +00:00 |
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test_lib_cdc.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_lib_coding.py
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formal→asserts
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2019-08-19 20:23:24 +00:00 |
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test_lib_fifo.py
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lib.fifo: handle depth=0, elaborating to a dummy FIFO with no logic.
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2019-09-23 12:27:59 +00:00 |
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test_lib_io.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_sim.py
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hdl.mem: use 1 as reset value for ReadPort.en.
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2019-09-20 19:51:13 +00:00 |
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tools.py
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_toolchain,build.plat,vendor.*: add required_tools list and checks.
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2019-08-31 00:05:47 +00:00 |
