whitequark c9879c795b build.{dsl,res,plat}: apply clock constraints to signals, not resources. ... This adds the Clock() build DSL element, and adds a resource manager function add_clock_constraint() that takes a Pin or a Signal. Note that not all platforms, in particular not any nextpnr platforms at the moment, can add constraints on arbitrary signals. Fixes #86.		2019-06-05 08:52:30 +00:00
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__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
lattice_ice40.py	build.{dsl,res,plat}: apply clock constraints to signals, not resources.	2019-06-05 08:52:30 +00:00