whitequark f05bd2a137 hdl.mem: allow omitting memory simulation logic. ... Trying to transform very large arrays is slow.		2018-12-24 11:53:59 +00:00
..
__init__.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
ast.py	hdl.mem: implement memories.	2018-12-21 01:53:32 +00:00
cd.py	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00
dsl.py	hdl, back: add and use SignalSet/SignalDict.	2018-12-17 17:21:29 +00:00
ir.py	hdl.ir: flatten hierarchy based on memory accesses, too.	2018-12-22 21:43:46 +00:00
mem.py	hdl.mem: allow omitting memory simulation logic.	2018-12-24 11:53:59 +00:00
xfrm.py	hdl.xfrm, back.rtlil: implement and use LHSGroupFilter.	2018-12-24 02:17:28 +00:00