amaranth/nmigen
whitequark b65e11f38f sim: split into base, core, and engines.
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.

This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.

This commit completely rearranges simulation code.
  1. sim._base defines internal simulation interfaces. The clarity of
     these internal interfaces is important because simulation
     engines mix and match components to provide a consistent API
     regardless of the chosen engine.
  2. sim.core defines the external simulation interface: the commands
     and the simulator facade. The facade provides a single entry
     point and, when possible, validates or lowers user input.
     It also imports built-in simulation engines by their symbolic
     name, avoiding eager imports of pyvcd or ctypes.
  3. sim.xxxsim (currently, only sim.pysim) defines the simulator
     implementation: time and state management, process scheduling,
     and waveform dumping.

The new simulator structure has none of the downsides of the old one.

See #324.
2020-08-27 11:52:31 +00:00
..
_toolchain _toolchain.cxx: work around PyPy missing LDCXXSHARED sysconfig variable. 2020-08-27 06:53:14 +00:00
back sim: split into base, core, and engines. 2020-08-27 11:52:31 +00:00
build build.run: implement SSH remote builds using Paramiko. 2020-08-26 22:49:49 +00:00
compat sim: split into base, core, and engines. 2020-08-27 11:52:31 +00:00
hdl hdl.ast: clarify exception message for out of bounds indexing. 2020-08-27 01:14:05 +00:00
lib lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=. 2020-08-26 03:19:13 +00:00
sim sim: split into base, core, and engines. 2020-08-27 11:52:31 +00:00
test nmigen.test.utils: restore FHDLTestCase to gracefully deprecate it. 2020-08-27 00:46:50 +00:00
vendor sim: split into base, core, and engines. 2020-08-27 11:52:31 +00:00
__init__.py Gracefully handle missing dependencies. 2020-07-01 07:00:02 +00:00
_unused.py _unused: extract must-use logic from hdl.ir. 2020-02-01 01:35:05 +00:00
_utils.py hdl.ir: allow disabling UnusedElaboratable warning in file scope. 2019-10-26 06:17:14 +00:00
asserts.py hdl.ast,back.rtlil: implement Cover. 2019-09-03 01:32:24 +00:00
cli.py cli: Improve help texts 2020-08-22 14:41:37 +00:00
rpc.py rpc: add public Records as module ports. 2019-09-30 18:28:21 +00:00
tracer.py tracer: fix get_var_name() to work on toplevel attributes. 2020-05-17 19:51:58 +00:00
utils.py {,_}tools→{,_}utils 2019-10-13 18:53:38 +00:00