12beda6e5b
Verilog has an edge case where an `always @*` process, which is used to describe a combinatorial function procedurally, may not execute at time zero because none of the signals in its implicit sensitivity list change, i.e. when the process doesn't read any signals. This causes the wires driven by the process to stay undefined. The workaround to this problem (assuming SystemVerilog `always_comb` is not available) is to introduce a dummy signal that changes only at time zero and is optimized out during synthesis. nMigen has had its own workaround, `$verilog_initial_trigger`, for a while. However, `proc_prune`, while increasing readability, pulls references to this signal out of the process. Because of this, a similar workaround was implemented in Yosys' `write_verilog` itself. This commit ensures we use our workaround on versions of Yosys without the updated `write_verilog`, and Yosys' workaround on later versions. Fixes #418.
54 lines
2.2 KiB
Python
54 lines
2.2 KiB
Python
from .._toolchain.yosys import *
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from . import rtlil
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__all__ = ["YosysError", "convert", "convert_fragment"]
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def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog_opts=()):
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# this version requirement needs to be synchronized with the one in setup.py!
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yosys = find_yosys(lambda ver: ver >= (0, 9))
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yosys_version = yosys.version()
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script = []
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script.append("read_ilang <<rtlil\n{}\nrtlil".format(rtlil_text))
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if yosys_version >= (0, 9, 3468):
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# Yosys >=0.9+3468 (since commit f3d7e9a1) emits Verilog without a possible sim/synth
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# mismatch, making $verilog_initial_trigger unnecessary.
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script.append("delete w:$verilog_initial_trigger")
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script.append("proc_prune")
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script.append("proc_init")
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script.append("proc_arst")
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script.append("proc_dff")
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script.append("proc_clean")
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script.append("memory_collect")
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if strip_internal_attrs:
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attr_map = []
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attr_map.append("-remove generator")
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attr_map.append("-remove top")
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attr_map.append("-remove src")
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attr_map.append("-remove nmigen.hierarchy")
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attr_map.append("-remove nmigen.decoding")
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script.append("attrmap {}".format(" ".join(attr_map)))
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script.append("attrmap -modattr {}".format(" ".join(attr_map)))
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script.append("write_verilog -norename {}".format(" ".join(write_verilog_opts)))
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return yosys.run(["-q", "-"], "\n".join(script),
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# At the moment, Yosys always shows a warning indicating that not all processes can be
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# translated to Verilog. We carefully emit only the processes that *can* be translated, and
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# squash this warning. Once Yosys' write_verilog pass is fixed, we should remove this.
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ignore_warnings=True)
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def convert_fragment(*args, strip_internal_attrs=False, **kwargs):
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rtlil_text, name_map = rtlil.convert_fragment(*args, **kwargs)
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return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs), name_map
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def convert(*args, strip_internal_attrs=False, **kwargs):
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rtlil_text = rtlil.convert(*args, **kwargs)
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return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs)
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