b65e11f38f
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.
This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.
This commit completely rearranges simulation code.
1. sim._base defines internal simulation interfaces. The clarity of
these internal interfaces is important because simulation
engines mix and match components to provide a consistent API
regardless of the chosen engine.
2. sim.core defines the external simulation interface: the commands
and the simulator facade. The facade provides a single entry
point and, when possible, validates or lowers user input.
It also imports built-in simulation engines by their symbolic
name, avoiding eager imports of pyvcd or ctypes.
3. sim.xxxsim (currently, only sim.pysim) defines the simulator
implementation: time and state management, process scheduling,
and waveform dumping.
The new simulator structure has none of the downsides of the old one.
See #324.
55 lines
1.6 KiB
Python
55 lines
1.6 KiB
Python
import functools
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import inspect
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from collections.abc import Iterable
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from ...hdl.cd import ClockDomain
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from ...hdl.ir import Fragment
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from ...sim import *
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__all__ = ["run_simulation", "passive"]
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def run_simulation(fragment_or_module, generators, clocks={"sync": 10}, vcd_name=None,
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special_overrides={}):
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assert not special_overrides
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if hasattr(fragment_or_module, "get_fragment"):
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fragment = fragment_or_module.get_fragment()
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else:
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fragment = fragment_or_module
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fragment = Fragment.get(fragment, platform=None)
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if not isinstance(generators, dict):
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generators = {"sync": generators}
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if "sync" not in fragment.domains:
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fragment.add_domains(ClockDomain("sync"))
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sim = Simulator(fragment)
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for domain, period in clocks.items():
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sim.add_clock(period / 1e9, domain=domain)
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for domain, processes in generators.items():
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def wrap(process):
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def wrapper():
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yield from process
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return wrapper
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if isinstance(processes, Iterable) and not inspect.isgenerator(processes):
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for process in processes:
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sim.add_sync_process(wrap(process), domain=domain)
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else:
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sim.add_sync_process(wrap(processes), domain=domain)
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if vcd_name is not None:
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with sim.write_vcd(vcd_name):
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sim.run()
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else:
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sim.run()
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def passive(generator):
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@functools.wraps(generator)
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def wrapper(*args, **kwargs):
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yield Passive()
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yield from generator(*args, **kwargs)
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return wrapper
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