b65e11f38f
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.
This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.
This commit completely rearranges simulation code.
1. sim._base defines internal simulation interfaces. The clarity of
these internal interfaces is important because simulation
engines mix and match components to provide a consistent API
regardless of the chosen engine.
2. sim.core defines the external simulation interface: the commands
and the simulator facade. The facade provides a single entry
point and, when possible, validates or lowers user input.
It also imports built-in simulation engines by their symbolic
name, avoiding eager imports of pyvcd or ctypes.
3. sim.xxxsim (currently, only sim.pysim) defines the simulator
implementation: time and state management, process scheduling,
and waveform dumping.
The new simulator structure has none of the downsides of the old one.
See #324.
333 lines
11 KiB
Python
333 lines
11 KiB
Python
from contextlib import contextmanager
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import itertools
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from vcd import VCDWriter
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from vcd.gtkw import GTKWSave
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from ..hdl import *
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from ..hdl.ast import SignalDict
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from ._base import *
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from ._pyrtl import _FragmentCompiler
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from ._pycoro import PyCoroProcess
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from ._pyclock import PyClockProcess
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__all__ = ["PySimEngine"]
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class _NameExtractor:
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def __init__(self):
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self.names = SignalDict()
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def __call__(self, fragment, *, hierarchy=("top",)):
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def add_signal_name(signal):
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hierarchical_signal_name = (*hierarchy, signal.name)
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if signal not in self.names:
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self.names[signal] = {hierarchical_signal_name}
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else:
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self.names[signal].add(hierarchical_signal_name)
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for domain_name, domain_signals in fragment.drivers.items():
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if domain_name is not None:
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domain = fragment.domains[domain_name]
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add_signal_name(domain.clk)
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if domain.rst is not None:
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add_signal_name(domain.rst)
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for statement in fragment.statements:
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for signal in statement._lhs_signals() | statement._rhs_signals():
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if not isinstance(signal, (ClockSignal, ResetSignal)):
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add_signal_name(signal)
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for subfragment_index, (subfragment, subfragment_name) in enumerate(fragment.subfragments):
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if subfragment_name is None:
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subfragment_name = "U${}".format(subfragment_index)
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self(subfragment, hierarchy=(*hierarchy, subfragment_name))
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return self.names
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class _VCDWriter:
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@staticmethod
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def timestamp_to_vcd(timestamp):
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return timestamp * (10 ** 10) # 1/(100 ps)
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@staticmethod
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def decode_to_vcd(signal, value):
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return signal.decoder(value).expandtabs().replace(" ", "_")
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def __init__(self, fragment, *, vcd_file, gtkw_file=None, traces=()):
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if isinstance(vcd_file, str):
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vcd_file = open(vcd_file, "wt")
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if isinstance(gtkw_file, str):
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gtkw_file = open(gtkw_file, "wt")
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self.vcd_vars = SignalDict()
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self.vcd_file = vcd_file
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self.vcd_writer = vcd_file and VCDWriter(self.vcd_file,
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timescale="100 ps", comment="Generated by nMigen")
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self.gtkw_names = SignalDict()
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self.gtkw_file = gtkw_file
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self.gtkw_save = gtkw_file and GTKWSave(self.gtkw_file)
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self.traces = []
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signal_names = _NameExtractor()(fragment)
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trace_names = SignalDict()
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for trace in traces:
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if trace not in signal_names:
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trace_names[trace] = {("top", trace.name)}
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self.traces.append(trace)
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if self.vcd_writer is None:
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return
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for signal, names in itertools.chain(signal_names.items(), trace_names.items()):
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if signal.decoder:
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var_type = "string"
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var_size = 1
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var_init = self.decode_to_vcd(signal, signal.reset)
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else:
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var_type = "wire"
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var_size = signal.width
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var_init = signal.reset
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for (*var_scope, var_name) in names:
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suffix = None
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while True:
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try:
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if suffix is None:
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var_name_suffix = var_name
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else:
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var_name_suffix = "{}${}".format(var_name, suffix)
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if signal not in self.vcd_vars:
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vcd_var = self.vcd_writer.register_var(
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scope=var_scope, name=var_name_suffix,
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var_type=var_type, size=var_size, init=var_init)
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self.vcd_vars[signal] = vcd_var
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else:
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self.vcd_writer.register_alias(
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scope=var_scope, name=var_name_suffix,
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var=self.vcd_vars[signal])
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break
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except KeyError:
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suffix = (suffix or 0) + 1
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if signal not in self.gtkw_names:
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self.gtkw_names[signal] = (*var_scope, var_name_suffix)
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def update(self, timestamp, signal, value):
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vcd_var = self.vcd_vars.get(signal)
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if vcd_var is None:
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return
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vcd_timestamp = self.timestamp_to_vcd(timestamp)
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if signal.decoder:
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var_value = self.decode_to_vcd(signal, value)
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else:
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var_value = value
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self.vcd_writer.change(vcd_var, vcd_timestamp, var_value)
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def close(self, timestamp):
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if self.vcd_writer is not None:
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self.vcd_writer.close(self.timestamp_to_vcd(timestamp))
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if self.gtkw_save is not None:
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self.gtkw_save.dumpfile(self.vcd_file.name)
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self.gtkw_save.dumpfile_size(self.vcd_file.tell())
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self.gtkw_save.treeopen("top")
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for signal in self.traces:
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if len(signal) > 1 and not signal.decoder:
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suffix = "[{}:0]".format(len(signal) - 1)
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else:
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suffix = ""
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self.gtkw_save.trace(".".join(self.gtkw_names[signal]) + suffix)
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if self.vcd_file is not None:
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self.vcd_file.close()
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if self.gtkw_file is not None:
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self.gtkw_file.close()
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class _Timeline:
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def __init__(self):
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self.now = 0.0
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self.deadlines = dict()
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def reset(self):
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self.now = 0.0
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self.deadlines.clear()
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def at(self, run_at, process):
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assert process not in self.deadlines
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self.deadlines[process] = run_at
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def delay(self, delay_by, process):
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if delay_by is None:
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run_at = self.now
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else:
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run_at = self.now + delay_by
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self.at(run_at, process)
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def advance(self):
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nearest_processes = set()
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nearest_deadline = None
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for process, deadline in self.deadlines.items():
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if deadline is None:
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if nearest_deadline is not None:
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nearest_processes.clear()
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nearest_processes.add(process)
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nearest_deadline = self.now
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break
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elif nearest_deadline is None or deadline <= nearest_deadline:
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assert deadline >= self.now
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if nearest_deadline is not None and deadline < nearest_deadline:
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nearest_processes.clear()
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nearest_processes.add(process)
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nearest_deadline = deadline
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if not nearest_processes:
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return False
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for process in nearest_processes:
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process.runnable = True
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del self.deadlines[process]
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self.now = nearest_deadline
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return True
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class _PySignalState(BaseSignalState):
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__slots__ = ("signal", "curr", "next", "waiters", "pending")
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def __init__(self, signal, pending):
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self.signal = signal
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self.pending = pending
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self.waiters = dict()
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self.curr = self.next = signal.reset
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def set(self, value):
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if self.next == value:
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return
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self.next = value
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self.pending.add(self)
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def commit(self):
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if self.curr == self.next:
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return False
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self.curr = self.next
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awoken_any = False
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for process, trigger in self.waiters.items():
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if trigger is None or trigger == self.curr:
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process.runnable = awoken_any = True
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return awoken_any
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class _PySimulation(BaseSimulation):
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def __init__(self):
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self.timeline = _Timeline()
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self.signals = SignalDict()
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self.slots = []
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self.pending = set()
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def reset(self):
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self.timeline.reset()
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for signal, index in self.signals.items():
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self.slots[index].curr = self.slots[index].next = signal.reset
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self.pending.clear()
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def get_signal(self, signal):
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try:
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return self.signals[signal]
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except KeyError:
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index = len(self.slots)
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self.slots.append(_PySignalState(signal, self.pending))
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self.signals[signal] = index
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return index
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def add_trigger(self, process, signal, *, trigger=None):
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index = self.get_signal(signal)
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assert (process not in self.slots[index].waiters or
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self.slots[index].waiters[process] == trigger)
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self.slots[index].waiters[process] = trigger
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def remove_trigger(self, process, signal):
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index = self.get_signal(signal)
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assert process in self.slots[index].waiters
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del self.slots[index].waiters[process]
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def wait_interval(self, process, interval):
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self.timeline.delay(interval, process)
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def commit(self):
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converged = True
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for signal_state in self.pending:
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if signal_state.commit():
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converged = False
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self.pending.clear()
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return converged
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class PySimEngine(BaseEngine):
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def __init__(self, fragment):
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self._state = _PySimulation()
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self._timeline = self._state.timeline
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self._fragment = fragment
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self._processes = _FragmentCompiler(self._state)(self._fragment)
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self._vcd_writers = []
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def add_coroutine_process(self, process, *, default_cmd):
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self._processes.add(PyCoroProcess(self._state, self._fragment.domains, process,
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default_cmd=default_cmd))
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def add_clock_process(self, clock, *, phase, period):
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self._processes.add(PyClockProcess(self._state, clock,
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phase=phase, period=period))
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def reset(self):
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self._state.reset()
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for process in self._processes:
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process.reset()
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def _step(self):
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# Performs the two phases of a delta cycle in a loop:
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converged = False
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while not converged:
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# 1. eval: run and suspend every non-waiting process once, queueing signal changes
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for process in self._processes:
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if process.runnable:
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process.runnable = False
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process.run()
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for vcd_writer in self._vcd_writers:
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for signal_state in self._state.pending:
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vcd_writer.update(self._timeline.now,
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signal_state.signal, signal_state.next)
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# 2. commit: apply every queued signal change, waking up any waiting processes
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converged = self._state.commit()
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def advance(self):
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self._step()
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self._timeline.advance()
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return any(not process.passive for process in self._processes)
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@property
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def now(self):
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return self._timeline.now
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@contextmanager
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def write_vcd(self, *, vcd_file, gtkw_file, traces):
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vcd_writer = _VCDWriter(self._fragment,
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vcd_file=vcd_file, gtkw_file=gtkw_file, traces=traces)
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try:
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self._vcd_writers.append(vcd_writer)
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yield
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finally:
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vcd_writer.close(self._timeline.now)
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self._vcd_writers.remove(vcd_writer)
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