whitequark bcdc280a87 hdl.ast, back.rtlil: add source locations to anonymous wires. ... This might help with propagation of locations through optimizer passes, since not all of them take care to preserve cells at all, but usually wires stay intact when possible. Also fixes incorrect source location on value.part().		2019-08-03 12:51:57 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: correctly add gtkwave traces for signals with decoders.	2019-07-12 13:35:44 +00:00
rtlil.py	hdl.ast, back.rtlil: add source locations to anonymous wires.	2019-08-03 12:51:57 +00:00
verilog.py	back.verilog: run proc_prune for much cleaner output.	2019-07-09 19:28:09 +00:00