whitequark bcdc280a87 hdl.ast, back.rtlil: add source locations to anonymous wires. ... This might help with propagation of locations through optimizer passes, since not all of them take care to preserve cells at all, but usually wires stay intact when possible. Also fixes incorrect source location on value.part().		2019-08-03 12:51:57 +00:00
..
back	hdl.ast, back.rtlil: add source locations to anonymous wires.	2019-08-03 12:51:57 +00:00
build	build.run: Ensure batch script returns proper error code.	2019-07-14 17:43:33 +00:00
compat	compat.genlib.fsm: fix after commit dac62754.	2019-07-08 10:12:26 +00:00
hdl	hdl.ast, back.rtlil: add source locations to anonymous wires.	2019-08-03 12:51:57 +00:00
lib	lib.fifo: fix typo.	2019-07-15 14:12:33 +00:00
test	hdl.ir: warn if .elaborate() returns None.	2019-08-03 12:30:39 +00:00
vendor	vendor: don't emit duplicate iobuf submodule names.	2019-07-21 07:49:21 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: add PyPy support to get_var_name().	2019-07-09 07:29:01 +00:00