whitequark bfbeca4584 back.rtlil: don't name-prefix signals connected to instance ports. ... This gives particularly pathological results on IO buffers, like: connect \D_OUT_0 \user_led_0_user_led_0__o Since subfragment signals are name-prefixed because this works well for signals propagated upwards across hierarchy, this is never desirable for instances.		2019-07-08 10:48:07 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: create unique ResetSynchronizer internal domains.	2019-06-28 08:34:43 +00:00
rtlil.py	back.rtlil: don't name-prefix signals connected to instance ports.	2019-07-08 10:48:07 +00:00
verilog.py	back.verilog: allow stripping the src attribute, for cleaner output.	2019-04-22 14:59:53 +00:00