whitequark bfbeca4584 back.rtlil: don't name-prefix signals connected to instance ports. ... This gives particularly pathological results on IO buffers, like: connect \D_OUT_0 \user_led_0_user_led_0__o Since subfragment signals are name-prefixed because this works well for signals propagated upwards across hierarchy, this is never desirable for instances.		2019-07-08 10:48:07 +00:00
..
back	back.rtlil: don't name-prefix signals connected to instance ports.	2019-07-08 10:48:07 +00:00
build	build.{dsl,res}: allow removing attributes from subsignals.	2019-07-08 10:42:10 +00:00
compat	compat.genlib.fsm: fix after commit dac62754.	2019-07-08 10:12:26 +00:00
hdl	hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.	2019-07-08 10:26:49 +00:00
lib	hdl.mem: use read_port(domain="comb") for asynchronous read ports.	2019-07-01 19:56:49 +00:00
test	build.{dsl,res}: allow removing attributes from subsignals.	2019-07-08 10:42:10 +00:00
vendor	vendor.xilinx_7series: generate also binary bitfile.	2019-07-07 21:36:32 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00