whitequark c6a0761b3a hdl.ir: accept LHS signals like slices as Instance io ports. ... This is unlikely to work with anything except Slice and Cat, but there's no especially good place to enforce it. (Maybe in Instance?)		2019-06-03 02:39:14 +00:00
..
back	back.rtlil: allow specifying platform for convert().	2019-05-26 17:10:56 +00:00
build	build.{res,plat}: propagate extras to pin fragment factories.	2019-06-03 01:58:43 +00:00
compat	Add import so that Tristate.elaborate builds	2019-05-20 16:34:31 +00:00
hdl	hdl.ir: accept LHS signals like slices as Instance io ports.	2019-06-03 02:39:14 +00:00
lib	lib.io: add a name argument to the Pin constructor.	2019-04-24 22:02:20 +00:00
test	hdl.ir: accept LHS signals like slices as Instance io ports.	2019-06-03 02:39:14 +00:00
vendor	build.dsl: require a dict for extras instead of a stringly array.	2019-06-02 23:36:21 +00:00
__init__.py	Add versioneer.	2019-05-26 11:20:13 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	formal: extract from toplevel module.	2019-01-17 01:43:07 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00